MauryaHub PYQ Practice

Computer Systems Design · End Term · Sep 2023 · FN

Computer Systems Design · End Term · Sep 2023 FN

← Course papers · Start practice / exam

Questions and published explanations below are available without starting a test. Some questions may not have a published solution yet.

0 / 20 published solutions

Question 2 MCQ · 1.0 marks

In a system with 17 unique states, 4 flip-flops are sufficient to represent all states.
6406532340188.
TRUE
6406532340189.
FALSE

A published solution is not available for this question yet.

Report a correction for Q2

Question 3 MCQ · 1.0 marks

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 1.
6406532340190.
TRUE
6406532340191.
FALSE

A published solution is not available for this question yet.

Report a correction for Q3

Question 4 MCQ · 1.0 marks

In a master-slave J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.
6406532340192.
TRUE
6406532340193.
FALSE

A published solution is not available for this question yet.

Report a correction for Q4

Question 5 MCQ · 1.0 marks

An SOP expression does not translate to the optimized circuit implementation.
6406532340194.
TRUE
6406532340195.
FALSE

A published solution is not available for this question yet.

Report a correction for Q5

Question 6 MCQ · 1.0 marks

In a decoder, at any point, exactly one of the outputs is 1 and all the rest are 0s.
6406532340196.
TRUE
6406532340197.
FALSE

A published solution is not available for this question yet.

Report a correction for Q6

Question 7 NAT · 3.0 marks

What is the minimum number of 4:1 multiplexers required to design a circuit that implements the function F(X,Y,Z) = (1,3,5,6). Assume X, Y, and Z as well as their complements to be available.

A published solution is not available for this question yet.

Report a correction for Q7

Question 8 NAT · 3.0 marks

Given that **NOT**, 2-input **AND/OR** gates have delays of 1 ns, what will be the maximum delay of a **3x8** decoder circuit? Note: if the answer is 1 ns, write 1.

A published solution is not available for this question yet.

Report a correction for Q8

Question 9 NAT · 3.0 marks

A 1-bit comparator takes two input bits and outputs **1** if they are equal, and **0** otherwise. What is the minimum number of 2-input **NAND** gates needed to design such a comparator?

A published solution is not available for this question yet.

Report a correction for Q9

Question 10 NAT · 3.0 marks

A circuit has three inputs (**A**, **B** and **C**) and a single output Y. Y is set to logic one if B is equals logic zero, otherwise **Y** is set to logic zero. What is the minimum number of minterms to be present in the SOP expression for **Y**?

A published solution is not available for this question yet.

Report a correction for Q10

Question 11 NAT · 3.0 marks

Source diagram or notation

A published solution is not available for this question yet.

Report a correction for Q11

Question 12 NAT · 3.0 marks

Consider a mod-15 down counter with an initial state of 0000. What will be the state of the counter after 32 clock pulses?

A published solution is not available for this question yet.

Report a correction for Q12

Question 13 NAT · 3.0 marks

Source diagram or notation

A published solution is not available for this question yet.

Report a correction for Q13

Question 14 SHORT_TEXT · 3.0 marks

Source diagram or notation

A published solution is not available for this question yet.

Report a correction for Q14

Question 15 NAT · 3.0 marks

Source diagram or notation

A published solution is not available for this question yet.

Report a correction for Q15

Question 16 NAT · 3.0 marks

If we implement a simple memory array with 16-bit addressability and an address space size of 64, then what would be the total size of the memory (in bytes)?

A published solution is not available for this question yet.

Report a correction for Q16

Question 17 SHORT_TEXT · 3.0 marks

Source diagram or notation

A published solution is not available for this question yet.

Report a correction for Q17

Question 18 NAT · 3.0 marks

Let a processor contain 64 registers in its register file. Consider that the ALU is capable of performing 6 different operations: addition, subtraction, AND, NOT, XOR and XNOR. What is the minimum number of bits required by an instruction in order to perform addition between two operands stored in the register file and then store the result in the register containing the first operand?

A published solution is not available for this question yet.

Report a correction for Q18

Question 19 NAT · 3.0 marks

Perform 2’s complement subtraction of two number A = 17, B = 24. What is the result of A - B in 8- bit binary format? (Note: Don’t use sign magnitude form.)

A published solution is not available for this question yet.

Report a correction for Q19

Question 20 MCQ · 3.0 marks

Source diagram or notation
6406532340209.Source diagram or notation
6406532340210.Source diagram or notation
6406532340211.Source diagram or notation
6406532340212.Source diagram or notation
6406532340213.Source diagram or notation

A published solution is not available for this question yet.

Report a correction for Q20

Question 21 MSQ · 3.0 marks

Which of the following Boolean functions can be used as a universal gate? Note: The boolean input zero and one are available.
6406532340202.Source diagram or notation
6406532340203.Source diagram or notation
6406532340204.Source diagram or notation
6406532340205.Source diagram or notation
      **Intro to BigData** **Section Id :** 64065349387 **Section Number :** 2 **Section type :** Online **Mandatory or Optional :** Mandatory **Number of Questions :** 24 **Number of Questions to be attempted :** 24 **Section Marks :** 50 **Display Number Panel :** Yes **Section Negative Marks :** 0

A published solution is not available for this question yet.

Report a correction for Q21