Computer Systems Design · Quiz 2 · Sep 2023

In a J-K flipflop, when J = 0 and K = 0, it toggles the flipflop’s state.

In a positive-edge-triggered D flipflop, if the D input is 0 and the clock signal transitions from low to high, Q output is 1.

In a NAND-based gated D latch, when the write enable input is 0, it denotes the Memory Hold state.

In a NAND-based gated D latch is edge-triggered, while a D flip-flop is level-sensitive.

Master-slave J-K flipflops are capable of preventing race-around conditions, whereas regular JK flipflops lack this capability.

The Boolean function for a combinational circuit with four inputs is represented by the following K-map.

Which literal will be present twice in the minimized SOP expression?

Consider the following expression:

Which of the following K-maps represents the expression correctly?

Consider a function, f which has four input variables (x, y, z, w). The function is defined to be high when the number is divided by 4 leaves the remainder of 1. Draw the Karnaugh Map (K-Map) for this function. Given inputs x, y, z, and w, along with their complements, if we want to implement the minimized expression using only 2-input NOR gates, what is the minimum number of NOR gates required?

A half adder is implemented using XOR and AND gates, and a full adder is implemented using two half adders and an OR gate. The propagation delay of AND gate is half of that of the XOR gate and the propagation delay of OR gate is 1.6 nanoseconds. If a 4-bit ripple carry adder is implemented using four full adders, then what will be the total propagation time of this adder circuit, considering the delay of one XOR gate is 4 nanoseconds.

In the circuit shown below, D1 and D2 are positive triggered D flipflops, x1 and x2 are input of D1 and D2 flipflop. Choose the correct timing diagram of the output Y.

We want to implement a 2-bit Gray code counter( an output sequence changing from 00 → 01 → 11 → 10 → 00) using the J-K flipflops as shown in the figure below. What should be the values of J1, K1, J2 and K2?

Consider the circuit diagram as shown below. Assuming it was initially cleared to 0, state the output Y for the next 4 clock pulses. Note: 1st one J-K flipflop 2nd one is D flipflop

We want to implement circuit that output sequence changing from 000 → 001 → 011 → 111 → 000 using J-K flipflops, as shown in the figure below. What combination of gates should GT1 and GT2 be?