Computer Systems Design · Quiz 2 · Jan 2024

In a J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.

A multiplexer is a digital circuit that selects one of several input signals and forwards it to a single output line.

In a NAND-based gated D latch, when the write enable input is 1, it denotes the Memory Hold state.

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 0.

Sequential circuits utilize feedback loops, while combinational circuits do not.

Consider the circuit diagram using j-K flipflop as shown below. Assuming it was initially cleared to 0, state the output Y for the next 4 clock pulses.

Choose the correct options

Based on below minterm, answer the given subquestions.

What will be the minimization expression?

Based on below minterm, answer the given subquestions.

If we want to design the given minterm using 2:1 multiplexers, what is the minimum number of multiplexers required?

Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 16 ns?

Consider the circuit consisting of three D flipflops and one NAND gate as shown below.The initial states are Q1=1, Q2=0, and Q3=1. What is the output (Q1,Q2,Q3) after 4 clock pulses?