Computer Systems Design · End Term · Sep 2025 · FN

A multiplexer is a combinational circuit that selects one input from multiple inputs and forwards it to a single output.

A JK flip-flop cannot store information without a continuous clock input.

In a 4-bit system, the two's complement of a binary number 1010 can be represented as -6.

A decoder performs the inverse operation of a multiplexer.

According to Moore's Law, the size of transistors on an integrated circuit doubles approximately every two years.

Given that NOT, 2-input AND/OR gates have delays of 1 ns, what will be the maximum delay of a 2x1 multiplexer circuit? Note: if the answer is 1 ns, write 1.

Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial states are Q1=1, Q2=0, and Q3=1. What is the output after (Q1,Q2,Q3) after 4 clock pulse?

Note: If answer if Q1=0, Q2=0,Q3=0, then write 000

A processor uses the following control word format:

How many registers can be addressed in the register bank?

Using 2's complement method, evaluate

where

and

. Give the answer in 8-bit binary format.

Choose the correct truth table according to the given Boolean expression:

Consider a common bus architecture containing memory and three registers: A, B, and C. The control word format is shown below.

What would be the control word if you intend to perform a register transfer from register A to register B? **Note:** Provide your answer in hexadecimal format (e.g., 0x3A).

A modern RISC processor contains 64 registers in its general-purpose register file. The Arithmetic Logic Unit (ALU) of the processor is capable of executing 16 distinct operations, which include standard arithmetic and logical functions. What is the

number of bits required by a

instruction to perform a bitwise

operation between two source operands located in the register file, and store the computational result back into a designated destination register?

Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 16 ns?

In the circuit shown below, D1 and D2 are positive edge triggered D flipflops, x1 and x2 are inputs of D1 and D2 flipflop. Choose the correct timing diagram of the output Y.

Consider the circuit diagram as shown below. Assuming it was initially cleared to 0, state the output(Y) for the next 4 clock pulses.

Consider the function given below:

If we want to implement the minimized expression using only 2-input NAND gates, what is the minimum number of NAND gates required?