Computer Systems Design · Quiz 2 · Sep 2025

Sequential circuit output depends only on current input while combinational circuit output depends on current and past input values

In a gated D-Latch, when write enable is 0, the latch holds its previous output regardless of the input.

In aJ-K flip flop, when J=1 and K=1, it toggles the flipflop’s state.

Consider the circuit diagram below with two D-flipflops, one XNOR gate and one NAND gate. Determine the correct sequence of output states. Note: initially D1 is in the set and D2 is in the reset state LSB

Consider the circuit shown below. Choose the valid timing diagram that corresponds to the circuit. Y D flip-flop Figure 1: Circuit Diagram

Consider the following circuit. Logic ox—> afp— Figure 2: Logic Circuit Given the truth table below, determine the equation for logic in terms of A, B, and Q,. ATBY Quit 0/0} Qn O11) O 1/0] 1{1] Qn

Answer the following question based on given timing diagram. Output(Y) Figure 3: Timing Diagram Given that we only have 2-input NOR gates are available, what is the minimum number of NOR gates required to represent a circuit whose output timing diagram matches as Y?

A positive-edge triggered D flip-flop is initially in the reset state (Q = 0). The input signal D and the clock signal are shown below: Clock period = 10ns D=1 from t=12ns to t=22ns,t=31 nsto t = 35 ns, t = 40 ns to t=45 ns, and D=0 otherwise. Assume the flip-flop samples D at the rising edge of the clock, and each rising edge occurs at t = 0, 10,20,30,40,... ns. What will be the decimal equivalent of the 4-bit output sequence Q observed at t = 10,20, 30,40 ns?

Consider the circuit diagram using J-K flipflop as shown below. Assuming it is initially cleared to 0, state the output Y for the next 4 clock pulses.