Computer Systems Design · Quiz 2 · May 2026

In a J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.

A multiplexer is a digital circuit that selects one of the several input signals and forwards it to a single output line.

In a NAND-based gated D latch, when the write enable input is 0, it denotes the **Memory Hold** state.

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 1.

Sequential circuits do not utilize feedback loops, while combinational circuits do.

Consider a gated D-Latch constructed using NAND gates. The initial input (at t=0 ns) is D=1, and the write enable (WE) signal is high. The write enable toggles between high and low every 5ns, while the input D changes from 1 to 0 and back to 1 every 8ns. What will be the output Q after 24ns?

Consider the J-K flipflop circuit shown below. Assuming the flipflop is initially set to 1, what will be the output sequence Y for the next four clock pulses?

Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial states are Q1=0, Q2=0, and Q3=0. What is the output after (Q1,Q2,Q3) after 5th clock pulse?

If we want to design the given minterm F=

using 3-input NAND gates, what is the minimum number of NAND gates required?

If we want to design the given minterm F=

using 2:1 multiplexers, what is the minimum number of multiplexers required?

Choose the correct option:

For the circuit shown in Figure 1, D1 and D2 are positive-edge-triggered D flip-flops with inputs x1 and x2 respectively, and their outputs Q1, Q2 feed into an XOR gate to produce Y . Which of the following correctly gives the Boolean expression for Y and the condition under which Y = 1?

We want to implement a circuit that outputs the sequence changing from 00 → 11 → 10 → 01 → 00 using J-K flipflops, as shown in the figure below. What should be the values of J1, K1, J2 and K2?